1. Field of the Invention
The present invention relates to a slice circuit, and particularly to a slice circuit converting an FM demodulation output analog signal to a digital signal in an FSK (Frequency Shift Keying) demodulator of an FSK receiver.
2. Description of the Background Art
For various applications such as DECT (Digital European Cordless Telephone) and Bluetooth, an FSK demodulator uses a slice circuit as shown in FIG. 52.
Referring to FIG. 52, a conventional slice circuit 1100 includes an integrator 1120, a LPF (Low Pass Filter) 1130 and a comparator 1140.
Integrator 1120 includes resistances 1121 and 1123, a capacitor 1122 and an operational amplifier 1124. One end of resistance 1121 is connected to a node N20 and the other end is connected to an inverting input terminal of operational amplifier 1124, respectively. Capacitor 1122 is connected between a node N22 and a ground node GND. Resistance 1123 is connected between nodes N21 and N22.
Operational amplifier 1124 receives on its noninverting input terminal a signal carried on node N20, and receives on its inverting input terminal a signal carried on node N22. The signal on node N22 is equal to a signal produced by integrating an input signal by a low pass filter formed of resistance 1121 and capacitor 1122.
Accordingly, operational amplifier 1124 amplifies only high frequency components of or above a predetermined frequency in the input signal by a gain determined by resistances 1121 and 1123, and provides or passes components lower than the predetermined frequency as they are.
Low pass filter 1130 includes a resistance 1131, capacitors 1132 and 1133, and a switch 1134. Resistance 1131 is connected between nodes N20 and N23. Capacitor 1132 is connected between node N23 and ground node GND. Capacitor 1133 and switch 1134 are connected in series between node N23 and ground node GND. Capacitor 1132 is connected in parallel to capacitor 1133 and switch 1134.
When switch 1134 is off, low pass filter 1130 detects an average voltage of voltages forming the signal on node N20 by resistance 1131 and capacitor 1132. When switch 1134 is on, low pass filter 1130 detects an average voltage of voltages forming the signal on node N20 by resistance 1131 and capacitors 1132 and 1133.
Thus, low pass filter 1130 detects the average voltage of voltages forming the signal on node N20 while changing a capacitance by turning on and off switch 1134. Therefore, low pass filter 1130 has a larger time constant when switch 1134 is on.
Slice circuit 1100 receives an input signal subjected to FM demodulation by a frequency discriminator 1000, and converts the received input signal from an analog signal to a digital signal.
Therefore, integrator 1120 receives the input signal from frequency discriminator 1000 via an input terminal 1110, and amplifies only high frequency components, which have frequencies equal to or higher than a predetermined frequency, in the received input signal for providing it to the noninverting input terminal of comparator 1140.
Low pass filter 1130 receives the input signal from frequency discriminator 1000 via input terminal 1110, and detects the average voltage of voltages forming the received input signal. Low pass filter 1130 provides the detected average voltage to an inverting input terminal of comparator 1140.
Comparator 1140 receives on its noninverting input terminal the input signal amplified by integrator 1120, and receives the average voltage of the input signal on its inverting input terminal. Comparator 1140 compares the voltage of the input signal with the average voltage, and provides a signal at an H (logical high) level to an output terminal 1150 when the voltage of the input signal is higher than the average voltage. When the voltage of the input signal is equal to or lower than the average voltage, comparator 1140 provides a signal at an L (logical low) level to output terminal 1150.
As described above, slice circuit 1100 amplifies only high frequency components in the input signal subjected to the FM demodulation by frequency discriminator 1000, and converts the signal from the analog signal to the digital signal.
However, the conventional slice circuit suffers from the following problems.
(1) When the input signal demodulated by the frequency discriminator is accompanied by drift of DC offset changing fast, the slice circuit cannot follow such changes, and the input signal cannot be accurately converted from the analog signal to the digital signal.
(2) According to modulation conditions, when xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d continues, the input signal sent from the frequency discriminator keeps a uniform voltage value for a certain duration. When the slice circuit receives this input signal, comparator 1140 receives from integrator 1120 the voltage at substantially the same level as the voltage received from low pass filter 1130 so that the comparing operation in comparator 1140 cannot be performed accurately.
(3) When noise components of high frequencies are input, these noise components are erroneously detected as intended signal components.
Referring to FIG. 53, the foregoing problems (1)-(3) will now be described in greater detail. When an input signal INS accompanied by fast drift of DC offset, low pass filter 1130 of slice circuit 1100 cannot follow such fast changes, and provides a signal INDC indicating the average voltage of voltages forming input signal INS to the inverting input terminal of comparator 1140.
Thereby, the voltage level of signal INDC hardly crosses the voltage level of input signal INS for a period from timing t1 to timing t2, and comparator 1140 can hardly compare the voltage level of input signal INS with the voltage level of signal INDC. Consequently, comparator 1140 provides a signal DX1. Thus, slice circuit 1100 cannot accurately convert the input signal from the analog signal to the digital signal when the input signal is accompanied by the fast drift of DC offset.
When slice circuit 1100 receives components corresponding to components including a succession of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d according to the FSK modulation at or after timing t2, the voltage level of signal INDC approaches the voltage level of input signal INS, and the voltage level of input signal INS cannot be discriminated from the voltage level of signal INDC during a period from timing t3 to timing t4. Consequently, comparator 1140 cannot accurately compare the voltage level of input signal INS with the voltage level of signal INDC, and provides a signal DX1 including an error component DES1.
A gain of integrator 1120 may be increased for overcoming the problem of the above item (1). In this case, however, integrator 1120 provides an amplified signal INA having a larger amplitude than input signal INS. Thereby, the voltage level of signal INDC crosses the voltage level of amplified signal INA during the period between timing t1 and timing t2, and comparator 1140 provides a signal DX2. As described above, the problem of the foregoing item (1) can be overcome by increasing the gain of integrator 1120. However, if input signal INS contains noise components having the same frequency as the high frequency components to be amplified in integrator 1120, amplified signal INS contains amplified noise components, resulting in the problem of the foregoing item (3).
The conventional slice circuit 1100 is configured to overcome the problems of the above items (1) and (2) by turning off switch 1134 of low pass filter 1130 to reduce the time constant during an initial period of reception of the input signal, and by turning on switch 1134 to increase the time constant during a latter period of reception of the input signal. This is because the drift of DC offset is generally fast during the initial period of reception of the input signal, and the drift of DC offset is generally slow during the latter period of reception of the input signal.
Accordingly, by controlling the time constant of the low pass filter as described above, it is attempted to cope with the fast drift of DC offset during the initial reception period, and to delay the timing, at which the voltage level of signal INDC approaches the voltage level of input signal INS, during the latter reception period as far as possible.
However, even if the measures are attempted by increasing the time constant of low pass filter 1130 and delaying the approach of the output voltage of low pass filter 1130 to the output voltage of integrator 1120 as far as possible, these measures do not fundamentally overcome an erroneous inverting operation of comparator 1140. Thus, conventional slice circuit 1100 cannot overcome both the problems in the items (1) and (2) at the same time.
For removing the noise components contained in the input signal as far as possible, the gain in integrator 1120 may be reduced. In this case, however, the voltage level of signal INDC cannot cross the voltage level of input signal INS when the input signal is accompanied by the fast drift of DC offset as described above. Therefore, comparator 1140 cannot accurately provide the digital signal. Thus, conventional slice circuit 1100 cannot overcome both the problems in the items (1) and (3) at the same time.
Accordingly, an object of the invention is to provide a slice circuit, which can accurately convert an input signal from an analog signal to a digital signal even when the input signal contains fast drift of DC offset.
Another object of the invention is to provide a slice circuit, which can accurately convert an input signal from an analog signal to a digital signal by removing noises even when the input signal contains fast drift of DC offset.
According to the invention, a slice circuit receiving an input signal prepared by demodulating a receive signal subjected to frequency modulation in a predetermined manner and having a voltage level corresponding to the frequency modulation, and converting the received input signal from an analog signal to a digital signal, includes a signal processing circuit and a comparator.
The signal processing circuit produces, based on the input signal, one of a first processing signal formed of a first main signal and a first reference signal, a second processing signal formed of a second main signal and a second reference signal, and a third processing signal formed of the first main signal and the second reference signal.
The comparator compares the voltage level of the first main signal with the voltage level of the first reference signal to provide a digital signal having a voltage level corresponding to results of the comparison when receiving the first processing signal. The comparator compares the voltage level of the second main signal with the voltage level of the second reference signal to provide a digital signal having a voltage level corresponding to results of the comparison when receiving the second processing signal. Further, the comparator compares the voltage level of the first main signal with the voltage level of the second reference signal to provide a digital signal having a voltage level corresponding to results of the comparison when receiving the third processing signal.
The first main signal is a signal having an amplified high frequency component of or above a predetermined frequency and a DC component formed of a predetermined voltage level, or is a signal having the high frequency component and a DC component at a voltage level changing in accordance with the DC component in the input signal. The second main signal is a signal having the high frequency component and a DC component being the same as the DC component in the input signal. Further, the first reference signal is a signal having an average voltage obtained by smoothing the input signal as it is. The second reference signal is a signal at a voltage level lower than the average voltage.
According to the invention, therefore, the slice circuit can achieve all or some of the following three effects.
(a) Even when an input signal Vin contains the drift of DC offset, the drift of DC offset can be removed, and input signal Vin can be accurately followed and converted from an analog signal to a digital signal.
(b) Even when the input signal contains components formed of a succession of uniform voltage levels, the input signal can be accurately converted from an analog signal to a digital signal.
(c) Even when the input signal contains noise components, erroneous detection of noise components can be prevented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.